1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor dies. More specifically, the invention relates to patterning interconnect metal in a semiconductor die.
2. Background Art
In semiconductor die manufacturing, interconnect metal segments are formed in interconnect metal levels of a semiconductor die to provide connectivity between various circuit elements in the semiconductor die. The interconnect metal segments can be formed in a conventional metal etch process, which utilizes a plasma dry etch technique to pattern a layer of interconnect metal, such as aluminum, to form the interconnect metal segments.
The conventional metal etch process works adequately when the thickness of the interconnect metal segments is less than 4.0 microns and the spacing aspect ratio, which is equal to the height of the interconnect metal segments divided by the space between adjacent interconnect metal segments, is generally less than 2.0. However, when the thickness of the interconnect metal segments is greater than 4.0 microns and the spacing aspect ratio is greater than 2.5, the conventional metal etch process results in undesirable undercutting on sidewalls of the interconnect metal segments and/or under-etching between adjacent interconnect metal segments.
Undercutting occurs as a result of over-etching, which is utilized in the conventional metal etch process to ensure that all residue metal is removed between adjacent interconnect metal segments. By way of background, metal etches faster in open regions of a semiconductor die, where the spacing between adjacent interconnect metal segments is relatively large and the spacing aspect ratio is generally less than 2.0, in comparison to dense regions of the semiconductor die, where the spacing aspect ratio between adjacent closely-packed interconnect metal segments is generally greater than 2.5. The different between etch rates in open and dense regions of the semiconductor die is referred to as reactive ion etch (“RIE”) lag. As a result of RIE lag, a substantial amount of over-etch is required to clear out residue metal between interconnect metal segments in dense regions of the semiconductor die.
Semiconductor manufacturers have attempted to reduce undesirable undercutting by reducing the amount of over-etch in dense regions of the semiconductor die. However, reducing the amount of over-etch in dense regions of the semiconductor die can result in undesirable under-etching.
Thus, there is a need in the art for an effective method for patterning interconnect metal in dense regions of a semiconductor die.